1. Field of the Invention
The present invention generally relates to sample and hold circuits and A/D converter apparatuses. Particularly, the invention relates to a sample and hold circuit suitable for use in a process of converting an input analog voltage into a digital value, and an A/D circuit including the sample and hold circuit.
2. Description of the Related Art
A sample and hold circuit is known in which an operational amplifier is used for performing a sampling and holding operation. In this type of a sample and hold circuit, the operational amplifier often employs a MOS transistor input configuration having a high input impedance. The operational amplifier of the MOS transistor input configuration, however, tends to have a large offset voltage compared to an operational amplifier having a bipolar input configuration because the element threshold voltage of the MOS transistor tends to have large variations. A method of cancelling the input offset of an operational amplifier involves sampling two voltages by two different capacitors, inverting the polarities of the two sampled voltages simultaneously, and then supplying the polarity-inverted voltages to the operational amplifier (see Non-Patent Document 1, for example).    Non-Patent Document 1: ISSCC Dig. Tech. Papers, pp. 318-319, 2007
In the offset cancelling method according to Non-Patent Document 1, because the two voltages are sampled by the different capacitors, parasitic capacitances that exist on the operational amplifier input end of the two capacitors do not necessarily correspond to each other. Thus, if the above offset cancelling method is used in the conventional sample and hold circuit mentioned above, an error due to the mismatch of the parasitic capacitances between the two capacitors would remain without being cancelled as an input offset of the operational amplifier. As a result, an accurate sample-and-hold output may not be obtained.